Hi guys. I decide a little bit reverse SLI VSA interconnect. So, it's my view at first approach, based on vsa manual and some checking on v55 specimen:
http://www.naviburg.ru/tmp/1/2xsli.jpgQuestion is: why sli data bus is 26 bit width? is it normal?
here is some copy paste from manual:
Quote:AA_CLK AA Clock: This pin is used to clock data from the SLI/AA slave to the SLI/AA master. It is driven by the slave and recieved by the master. This has an internal pullup resistor.
AA_DATA[11:0] AA Data: This bus is used to transmit data from the SLI/AA slave to the SLI/AA master. It is driven by the slave and recieved by the master. Each pin has an internal pullup resistor.
AA_VALID AA Valid: This pin is used to indicate when SLI/AA data is available on the bus. It is driven by the slave and recieved by the master. This pin requires a pull-down. This pin has an internal pullup resistor.
DAC_CUR_SINK[2:0]DAC Current Sink: These pins are used to specify the full scale DAC current level. Each is connected to the DAC_CUR_SRC input of one slave. If there are less than three slaves, the unused pins (on the master) are not connected. On slaves, these pins are not
connected.
DAC_CUR_SRCDAC Current Source: This pin is a no-connect on the master. On a slave, it connects to the one of the three DAC_CUR_SINK[2:0] pins on the master.
PCI_FIFO_ST PCI Bus FIFO Stall: This is an output on SLI slaves and an input on the SLI master. The slaves can activate this signal to slow down the master when the slave FIFO is nearly full (the slave is bus snooping and cannot make TRDY active). This pin requires a pull-down resistor.
PCI_RDRDY PCI Bus Read Ready: This is an output on SLI slaves and an input on the SLI master. The slaves can activate this signal to indicate that data is not available for reads of AA data (all the slaves have to have data ready before the read can complete) or SLI data. This pin requires a pull-down resistor.
SLI_SYNC_IN SLI Sync In: This input connects to the SLI_SYNC_OUT pin of the previous chip in an SLI chain. This pin requires a pull-down resistor.
SLI_SYNCOUT SLI Sync Out: This output connects to the SLI_SYNC_IN pin of the next chip in an SLI chain. This pin requires a pull-down resistor.
SYNC_CLK_FBSLI Sync Clock Feedback: On the SLI master, this pin is grounded. On each SLI slave, this pin connects to the SYNC_CLK_OUT pin of the same chip through a trace that is the same length as the trace from the master’s SYNC_CLK_OUT.
SYNC_CLK_IN SLI Sync Clock In: On the SLI master, this pin is grounded. On each SLI slave, this pin is driven from the master’s SYNC_CLK_OUT.
SYNC_CLK_OUTSLI Sync Clock Out: On the SLI master, this pin is connected to the SYNC_CLK_IN pin of each SLI slave. This is a 12 mA driver and will very likely need a damping resistor very close to the pin. On each SLI slave, this pin is connected to the SYNC_CLK_FB of the
same chip. This trace length should be the same as the trace length from the master’s SYNC_CLK_OUT.
VSYNC_REF Vertical Sync Reference: This pin supplies a vertical sync reference from the SLI master to the SLI slaves. This is a 12 mA driver. |
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and here is muliplexed rest of data pins (with strange numeration and without any description):
Quote:VMI_HA0 C23 SLI/AA Data 8
VMI_HA1 D22 SLI/AA Data 9
VMI_HA2 C22 SLI/AA Data 10
VMI_HA3 B22 SLI/AA Data 11
VMI_RW_N E22 SLI/AA Data 24
VMI_DS_N E20 SLI/AA Data 25
VMI_RDY_N D21 SLI/AA Data 26
VMI_HD0 D23 SLI/AA Data 0
VMI_HD1 C26 SLI/AA Data 1
VMI_HD2 C25 SLI/AA Data 2
VMI_HD3 C24 SLI/AA Data 3
VMI_HD4 B24 SLI/AA Data 4
VMI_HD5 A24 SLI/AA Data 5
VMI_HD6 A23 SLI/AA Data 6
VMI_HD7 B23 SLI/AA Data 7 |
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Any thoughts?