***** Napalm and Napalm2 Release Note *****
========================================================================
9/14/00 - Napalm Ver. 1.18
Fixed bug with all extended modes coming up corrupted when going into
extended mode.  Bug is with Napalm2 SGRAMMODE value being programming
into Napalm.
Fixes PRS#15511

* OEM.INC *
Made the SGRAMMODE register setting coniditional compile for Napalm
and Napalm2.  Fixes problem with Napalm2 SGRAMMODE setting being used
on Napalm.
Fixes PRS#15511

========================================================================
9/12/00 - Napalm Ver. 1.17
Updated the BIOS build options to match the Napalm BOM in MRD ver 1.19.

* OEM.INC *
Removed the build option for the V5P901 AGP/SD/166MHz/No TV/No DVI/2 Way.
Change the MCLK for V5P848 to 166MHz.
Added a BIOS option for V4P906 AGP/SD/143MHz/No TV/No DVI/Single chip.

========================================================================
8/18/00 - Napalm Ver. 1.16 & Napalm2 Ver. 1.04
1) Fixed errors in BIOS default extended mode timings.
2) Fixed bug with BIOS GTF register programming routine.
3) Condensed the board name strings.

Napalm2 only changes.
1) Fixed bug in memory sizing routine.
2) Updated PCI device ID to 0Bh
3) Put in memory timings for 100MHz MCLK.

* DATA.ASM *
Added conditional compiled code to only print the string "Supported "
after the board name when compiling a TV and/or LCD BIOS.

* BIOSPARM.INC *
Updated the horizontal and vertical sync start and and positions for the
following modes: 640x400, 640x480, 800x600, 1024x768, 1280x1024, and
80x60 (Mode 108h).

* OEMPARM.INC *
Updated the horizontal and vertical sync start and and positions for the
following modes: 320x200, 320x240, 400x300, and 512x384.

* OEM.ASM *
In OEMGetMemSize, saved the memory size in AX.  This is a Napalm2 change
only.

In OEMFixupCRTC, decreased the vertical sync start and end values by one.
Only decreaced the horizontal sync start and end value by one when not
doing a 1024x768 mode.

Created the routine CheckIf1024Mode to check if we're a 1024x768 mode.
If 1024x768 mode, zero flag is set.


* OEMPOST.ASM *
In InitRegisters, change the Napalm2 DramInit0 register mask to
072000000h DramInit1 register mask to 0C3000000h. Added Napalm2 code
to do a mode set to the memory and to the DLLs on the DDR memory
only.


* OEM.INC *
Change the Napalm2 memory clock to 100MHz.

Shortened all the STR_OEMPRODUCT strings for the TV and LCD BIOSs.
Removed the words "with" and "support" from the string.
For example, changed the LCD BIOS from "Voodoo4 4800 with LCD support "
to "Voodoo4 4800 LCD ".

Added memory clock PLL settings for 210MHz, 200MHz, 170MHz, 125MHz, and
100MHz.

Changed the Napalm2 device ID to 0Bh.

Created Napalm2 conditional compiled code for DramInit settings.
For MCLKs below 143MHz, the following is used:
     DEFAULT_DRAMINIT0      equ      0807FE9A9h
     DEFAULT_DRAMINIT1      equ      040034031h
For MCLKs above or equal to 143MHz, the following is used:
     DEFAULT_DRAMINIT0      equ      0807FE9A9h
     DEFAULT_DRAMINIT1      equ      040030031h

Changed the Napalm2 DEFAULT_SGRAMMODE setting to 00002000h

========================================================================
8/14/00 - Napalm Ver. 1.15 & Napalm2 Ver. 1.03
Decreased the ampount time it took to execute video POST.
For a BIOS with no copyright message, video POST when from ~191 mSec to
~155 mSec.

* INIT.ASM *
In InitInfoVars, modified the setmode calls to not clear the screen and
only initilize the registers.

In the MonitorDetect routine, routine the code which initilizes the
RAMDAC to 00h.  A setmode call later in POST will re-initilize the DAC
to it's default value.

* OEMPOST.ASM *
In Patch32KRom, optimized the checksum routine to not reload the added
ROM during each iteration of the loop.  Started the ROM address at 00h
and had the LODSB automaticlly increament the address.

========================================================================

8/4/00 - Napalm Ver. 1.14
Updated BIOS build options to include the following boards:
V5P901 - AGP/SD/183 MHz/No TV/No LCD/V5-5800
V5P899 - AGP/SD/166 MHz/No TV/No LCD/V5-5500
V5P896 - PCI/SD/166 MHz/No TV/No LCD/V5-5500
V5P902 - AGP/SG/166 MHz/No TV/No LCD/V5-5000
V5P899 - AGP/SD/166 MHz/No TV/No LCD/V5-5500

Removed the following BIOS build options:
V5P874 - AGP/SG/166/No TV/No LCD/V5-5000
V5P847 - PCI/SG/166/No TV/No LCD/V5-5000
V5P884 - PCI/SD/166/With TV/With LCD/V4-4500

Change the memory clock for the V5P848 BIOS to 183 MHz

* OEM.INC *
Added build options for the following boards:
     V5P901, V5P899, V5P896, V5P902, V5P899

Removed build options for the following boards
     V5P874,      V5P847,      V5P884

Change the memory clock for the V5P848 to 183 MHz


========================================================================
8/2/00 - Napalm Ver. 1.13 & Napalm2 Ver. 1.02
Fixed bug with some CRT monitors booting monochrome.
Fixes PRS#15126

Fixed bug with booting to TV on BIOSs which has both TV and panel support.


* INIT.ASM *
Changed the Monitor Sense DAC value, Default_Trigger, from a 18h to 15h.
This fixes the problem with some CRT monitors booting monochrome.
Fixes PRS#15126

* VESA.ASM *
In the routine DDCWaitClockHigh, decreased the number of retries from
65536 to 256.  This decreased the time one had to wait for the TV to
boot on a combo TV and DVI BIOS.

* OEMPOST.ASM *
In the routine CheckForPanel, fixed bug with error checking.  This
fixed a bug in the combo TV and panel BIOS where the BIOS to booted
to the panel when only a TV attached.

* OEM.INC *
Changed DramInit0 to 0001EA9A9h.  Made tRP = 2, row precharge = 3 clocks.
========================================================================
7/21/00 - Ver. 1.12
Created compile flag to disable the display of the copyright message
during POST.

* OEM.INC *
Created the flag DisableCopyrightMsg to display tje copyright message.
This flag is enabled by the comple flag "-DTURN_OFF_COPYRIGHT_MSG"

* INIT.ASM *
In InitBIOS, conditionally compiled the code which display the
copyright banner.

========================================================================
6/29/00 - Ver. 1.11
Removed the modification of the V5P896 build - vidProcCfg[29:28]=00
Reset the Clock for the V5P869 to 166MHz.

* OEM.INC *
Reset the flags so V5P869 will build at 166MHz.

* OEMPOST.ASM *
Removed the following flag and code:
In InitRegisters, added conditional compiled code to clear
     VidProcCfg[29:28]=00 when compiling a V5P896 BIOS.  All
     other BIOSs have VidProcCfg[29:28]=11.
(All products have VidProcCfg[29:28]=11.)

========================================================================
6/16/00 - Ver. 1.10
Modified the V5P896 build option to have vidProcCfg[29:28]=00 and all other
BIOS builds have vidProcCfg[29:28] = 11.

* OEM.INC *
Created the flag Build_V5P896.  This flag is set only when compiling
     a V5P896 BIOS. 

* OEMPOST.ASM *
In InitRegisters, added conditional compiled code to clear
     VidProcCfg[29:28]=00 when compiling a V5P896 BIOS.  All
     other BIOSs have VidProcCfg[29:28]=11.


========================================================================
6/15/00 - Ver. 1.09
Removed build options for V5P847 and V5P874.  This reflects the current
version of the Napalm Board BIOS Names and Build opts.doc.

* OEM.INC *
Removed the build options for V5P847 and V5P874.ROM.

========================================================================
6/9/00 - Ver. 1.08
Added build for Assy# 0896 (VD5 5500 PCI) at 155MHz.

* OEM.INC *
Value of PLLCTRL1 set to 0x3F05 for 155MHz PCI assembly. Will not affect
any other assembly.

========================================================================
6/5/00 - Ver. 1.07
Fixed errors in VBE mode timings for 1024x768 graphics and 132xXX text
     modes.
     Fixes PRS# 14384 and 14386.

During POST, initilized I/O base address before calling OEMEnableExtentions.
     Fixes PRS#14303


* BIOSPARM.INC *
Made the sync polarities for 1024x768 both negative.  Timings now follow
   the      VESA/STB spec for this mode.
     Fixes PRS#14384

* OEMPARM.INC *
Fixed timing error in horizontal blank end, and horizontal sync start and
     end. Timings now follows the VESA/STB spec for this mode.
     Fixed PRS#14386

* OEMPOST.ASM *
In OEMInitWakeup, called InitIOBase before calling OEMEnableExtnsions.
   Fixes PRS#14303

========================================================================
5/15/00 - Ver. 1.06
Set VidProcCfg[29:28] = 11 to disable memory optimization.

* OEMPOST.ASM *
In InitRegisters, set VidProcCfg[29:28] = 11b.

* OEM.ASM *
In OemSetRegs, did a Read-Modify-Write of VidProcCfg.  Preserved bits
29-28.

========================================================================
5/08/00 - Ver. 1.05
Corrected VPD Checksum to allow for (ICT) Production BIOS programming

* MAIN.ASM *
Changed VPD Checksum from 0x85 to 0x79