Hello all,

all of us 3dfx Voodoo5 6000 people have the 6 pinned connector infront of our Xilinx chips and I do know that those pins were used to program that Xilinx chip, but what is the purpose of that Xilinx chip?

The ATi Radeon X1900 series have that chip as well:
http://hardwarelogic.com/articles/reviews/video%20cards/X1900_Crossfire/XiLink.jpg

and here the same type chip on the Voodoo5 6000's:
http://www.3dfx.ch/gallery/d/12803-1/V6K+Xilinx+close.jpg

Do both Xilinx chips have the same purpose, if so what purpose?

Cheers,

Ben Kenobi.

If you search on the website http://www.xilinx.com "XC9536", you find this:
http://direct.xilinx.com/bvdocs/appnotes/xapp103.pdf
or this:
http://www.xilinx.com/bvdocs/publications/ds120-1.pdf

it seems to be a programable chip.

yeah I know that it is programable I did state that hehe the 6 pins infront of it were used to program that chip, but there should a more logic purpose in a way like to keep the power feed and dataflow stable between all 4 VSA's , ram chips and HiNT PCI-PCI bridge chip or something?

By glancing at the PDF file links provided by @gtxe  -I'm assuming that it's a debug interface chip on BOTH cards that is used by engineers in the lab to test and fix BIOS bugs. ;)

Don't we also have the same thing on our 200SBi cards? I know the pin configuration is a bit different 2 rows of 3.

6 pins are JTAG interface.

Chip controlls the reset and 14MHz clock to VSA100. If 12 V power is not present, chips are sent to reset and 14MHz clock is removed.

what's that advantage of that 14Mhz clock since that the most VSA_100 chips run frequently @ 166Mhz ?

Sorry but I don't understand where the 14Mhz get's in and what it is needed for hehe :)

I think the 14mhz signal is for a test clock to each VSA-100 chip to produce a logic output to a debugger interface.

14.31818 is the ref. clock for internal PLLs

So is this correct then? Fout = 14.31818 mhz * (N + 2) / (M + 2) / (2 ^ K) to control the GRX Clock. What else does the ref. signal output to, the AGP speed or Sli clocks ???  and I would guess that the 6 pin interface would only be on proto-boards and not on final production boards or is it a standard method of Q.A. and trobleshooting??  

There are 2 PLLs connected to 14 MHz. First one to generate GRX clock, which is the same as MEM clock.
Second PLL generates the display clock.

There is also 3rd PLL that is connected to AGP (PCI) clock that one is used for phase recovery, it is not programmable.

JTAG port would be on all boards, it is necessary to program the Xilinx chip for the board to be functional.

hmm very interestig, but it's gett'n pretty nitty gritty for me now hehe what is a PLL? never heard of that, sorry Hank. :)

a PLL is a clock generator imho...

PLLs (phase locked loops) are electonic systems that compare the freq. for some application with a reference freq. and correct it. (PLLs include the application's ferq. generator)

In RL its quite more complex then I explained but just so that u get a picture. :P

As Hank said in our case here the Xilinx is the one providing those reference freq.s.

The Phased-Locked Loop (PLL) is an electronic feedback loop and It is found in many communication devices. The PLL circuit is to make a variable-frequency oscillator to lock in at a frequency (The GRX and Video clk for example ) and the phase angle (sine wave) of a standard frequency (14.3181 mhz)  used as a reference and I think using the Registers (flip flops) allows the software to program the Fout at 166 mhz or any other desire frequency you program into. With out this circuit, the Art of Overclocking our Voodoos would not exist!!!! (Unless you went old fashion and used a radio knob!!!)  ;~)

Hank mention that the AGP PLL is used for phase recovery (phase correction?) I wonder is this is the reason for the Voodoo5 can't do the AGP 4X mode correctly because of wandering frequency??? Please correct me if I am wrong....

wrote on 02.04.06 at 14:10:16:

I wonder is this is the reason for the Voodoo5 can't do the AGP 4X mode correctly because of wandering frequency??? Please correct me if I am wrong....

If I remember right it has to do with the master/slave chip setup which was not properly supported till the later AGP spec was released.

I suppose that the AGP4 thing was fixxed with the Rampage series, would the Rampage series have used the same type of SLI and same Xilinx chips as well?

VSA100 single chip board will do 4X AGP. Some eastern manufacturers goofed the design of the board so they are stuck at 2X.

Multichip board is only PCI subset of AGP, it will not use AGP extensions at all.

Rampage would have used 4X AGP even in multi chip configuration.

ah okay, what about dual core techniques was that in palnning as well, i don't meant two sepperate cores but dual core like Athlon64X2 that idea, that way the production costs would decrease also and performance might increase a little since that the latencies between cores and ram smaller is.

would 3dfx have used dualcore technology in the future?, because Ati and nVidia are still clumsing around with 2 pieces of PCB with each a sepperate core hah, I think 3dfx would just used the dualcore idea anayways, since thier ambitions for  designing the craziest idea's always was with them

8) ;D